This invention relates to the concept and the fabrication of a multi chip electronic module having a high density of interconnects and fabricated using integrated circuit processes on semiconductor or dielectric wafers. Such a package of individual integrated circuit and other elements, which may be described as a system on a package, can offer technical and economic advantages compared to a single fully integrated chip or to a conventional multi chip module.
In the assembly of integrated semiconductor circuit elements such as integrated circuit chips and other passive and active electrical components into a complete unit, these elements are typically mounted in an electronic package which provides for interconnection among the elements. Electronic packages typically provide a much lower density of interconnection and wiring than is available within an integrated circuit chip. Thus as many diverse functions as possible are often combined within single integrated circuit chips in order to make use of the dense multi layer chip wiring to maximize the functionality and performance of the complete unit. As the function performed by the unit increases in complexity, the chip size typically increases.
As the size of an integrated circuit chip becomes larger, the yield of satisfactory chips in a typical manufacturing process decreases exponential and the cost of the chip increases beyond acceptable limits. Furthermore, the diverse parts of the chip must all be fabricated using the same fabrication process, typically leading to difficult compromises. For example, combining logic and memory circuits on the same chip with a compromise process degrades logic performance and memory density compared to using the optimal process technology for each type of circuit. Integrating many diverse functions on a single chip also greatly increases design time. These problems can be avoided by using a number of smaller chips connected together in an electronic package, but performance may be degraded due to the lower interconnection capability of typical packages.
There has been some effort in the art, as illustrated in U.S. Pat. No. 6,025,638 to develop electronic packaging which provides a greater density of interconnects. This approach employs a complex fabrication process which uses materials and processes which are not typically practiced as part of semiconductor chip or package fabrication.
In addition to the considerations of chip size and partitioning, there also considerations in choosing electronic package materials and processes which are commonly practiced, well characterized, inexpensive, and simple. Some insight into such considerations are discussed in a publication titled xe2x80x9cSilicon Interposer Technology For High-Density Packagexe2x80x9d by Matsuo et al., in the Proceedings of the 50th IEEE Electronic Components and Technology Conference, 2000, pages 1455-1459; wherein the use of a silicon interposer attached to a single chip is advanced.
There are clear needs in the art for an electronic packaging capability that will operate to provide a high interconnect and wiring density between chips and which will allow the package to be fabricated using a simple technique involving commonly available fabrication processes and tools.
In the invention, a wafer of a semiconductor such as silicon or a dileetno such as glass is used as an electronic module package substrate. Conducting vias through the wafer and high density, inter and intra, chip contacts and wiring, are fabricated using conventional silicon wafer processing tools and processes available in the mt. The substrate may be chosen to have a similar thermal expansion coefficient as that of the chips mounted thereon. The use of vias through the substrate provides for a high density of connections exiting to the next level of packaging hierarchy, allows short paths for power and signals and improves power and ground distribution.